Electronic drive circuit

ABSTRACT

An electronic circuit includes an input configured to receive an input signal and an output configured to be coupled to load, an output transistor including a load path and a control node, the load path being connected between the output and a first supply node, a drive transistor including a load path and a control node, the load path being connected to the control node of the output transistor, a first electronic switch connected in series with the load path of the drive transistor, a biasing circuit including an internal impedance and connected between the control node of the drive transistor and the first supply node, and a control circuit configured to receive the input signal and to drive the first electronic switch based on the input signal.

PRIORITY CLAIM

This application claims priority to German Patent Application No. 102015 102 878.6 filed on 27 Feb. 2015, the content of the applicationincorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments of the present invention relate to an electronic circuit, inparticular an electronic drive circuit for driving a capacitive loadsuch as, for example, the gate of a transistor.

BACKGROUND

MOS transistors such as MOSFETs (Metal Oxide Semiconductor Field-EffectTransistors) or IGBTs (Insulated Gate Bipolar Transistors) are widelyused in automotive, industrial, or consumer electronic applications fordriving loads, converting power, or the like. MOS transistors arevoltage controlled devices that include an internal capacitance (oftenreferred to as gate-source capacitance) formed by a gate electrode, agate dielectric and body and source regions. The MOS transistor can beswitched on and off by charging and discharging the internalcapacitance, wherein switching on includes one of charging anddischarging the internal capacitance, and switching off includes theother one of charging and discharging the internal capacitance. Forexample, in an enhancement type MOS transistor, switching on the MOStransistor includes charging the internal capacitance and switching offthe MOS transistor includes discharging the internal capacitance.

Modern MOS transistors for switching electrical loads may have a voltageblocking capability of several 10V up to several 100V but may bedesigned to withstand voltages of only several volts, such as less than5V or even less than 3V at their internal capacitance (at the gatenode). Furthermore, it is desirable to switch those MOS transistors athigh frequency, that is, to charge and discharge the internalcapacitance at a high rate.

There is therefore a need for an electronic drive circuit that iscapable of driving a capacitive load at a high frequency withoutexceeding a predefined voltage threshold across the capacitive load.

SUMMARY

One embodiment relates to an electronic circuit. The electronic circuitincludes an input configured to receive an input signal and an outputconfigured to be coupled to load, an output transistor having a loadpath and a control node, wherein the load path is connected between theoutput and a first supply node, and a drive transistor having a loadpath and a control node, wherein the load path is connected to thecontrol node of the output transistor. A first electronic switch isconnected in series with the load path of the drive transistor. Abiasing circuit having an internal impedance is connected between thecontrol node of the drive transistor and the first supply node. Theelectronic circuit further includes a control circuit configured toreceive the input signal and to drive the first electronic switch basedon the input signal.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples are explained below with reference to the drawings. Thedrawings serve to illustrate certain principles, so that only aspectsnecessary for understanding these principles are illustrated. Thedrawings are not to scale. In the drawings the same reference charactersdenote like features.

FIG. 1 shows an electronic drive circuit according to one embodiment;

FIG. 2 shows timing diagrams of an input signal and of signals occurringin the electronic drive circuit shown in FIG. 1;

FIG. 3 shows timing diagrams illustrating one way of operation of theelectronic drive circuit shown in FIG. 1;

FIG. 4 shows one embodiment of a biasing circuit in the electronic drivecircuit;

FIG. 5 shows one embodiment of a voltage regulator in the biasingcircuit shown in FIG. 4 in greater detail;

FIG. 6 shows an electronic drive circuit according to anotherembodiment;

FIG. 7 shows timing diagrams illustrating one way of operation of theelectronic drive circuit shown in FIG. 1; and

FIG. 8 shows an electronic drive circuit according to yet anotherembodiment.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings. The drawings form a part of the description andby way of illustration show specific embodiments in which the inventionmay be practiced. It is to be understood that the features of thevarious embodiments described herein may be combined with each other,unless specifically noted otherwise.

FIG. 1 shows an electronic drive circuit according to one embodiment.This electronic drive circuit is configured to drive a load. Inparticular, the electronic drive circuit is configured to drive acapacitive load. For example, the capacitive load is an MOS transistor.An MOS transistor, such as a MOSFET or an IGBT, is a voltage controlledsemiconductor device that switches on or off dependent on a chargingstate of an internal gate-source capacitance. Just for the purpose ofillustration, FIG. 1 shows a capacitive load Z implemented as a MOSFET,in particular, an n-type enhancement MOSFET. However, this is only anexample. Any other type of MOS-transistor may be driven by theelectronic drive circuit as well. The internal gate-source capacitanceof this MOSFET is represented by a capacitor CGS connected between agate node G and a source node S of the MOSFET Z.

Referring to FIG. 1, the electronic drive circuit includes an input 11configured to receive an input signal S_(IN) and an output 12 configuredto be coupled to a load Z. In case the load Z is a MOSFET (as shown inFIG. 1) the output 12 of the electronic drive circuit is connected tothe gate node of the MOSFET.

The electronic drive circuit further includes an output transistor 1 ₁,a drive transistor 2 ₁, and a first electronic switch 3 ₁. The outputtransistor 1 ₁ includes a load path connected between the output 12 anda first supply node 13 ₁, and a control node. The drive transistor 2 ₁includes a control node, and a load path connected to the control nodeof the output transistor 1 ₁ and connected in series with the firstelectronic switch 3 ₁. The first electronic switch 3 ₁ is connectedbetween a second supply node 14 ₁ and the load path of the drivetransistor 2 ₁.

The electronic circuit may include a second electronic switch 6 ₁connected between the control node of the output transistor 1 ₁ and thefirst supply node 13 ₁. Optionally, a resistor 7 ₁ (illustrated indashed lines in FIG. 1) is connected in parallel with the secondelectronic switch 6 ₁ and, therefore, between the control node of theoutput transistor 1 ₁ and the first supply node 13 ₁.

A biasing circuit 4 ₁ is connected between the control node of the drivetransistor 2 ₁ and the first supply node 13 ₁. The biasing circuit 4 ₁includes a voltage source 41 ₁ configured to provide a biasing voltageV4 ₁, and an internal impedance 42 ₁. The biasing circuit 4 ₁ isexplained in greater detail herein below. A control circuit 5 ₁ isconfigured to receive the input signal S_(IN) and to drive the firstelectronic switch 3 ₁ and the second electronic switch 6 ₁ based on theinput signal S_(IN).

The circuit elements explained above, that is, the output transistor 1₁, the drive transistor 2 ₁, the first electronic switch 3 ₁, thebiasing circuit 4 ₁, the control circuit 5 ₁, the second electronicswitch 6 ₁, and the optional resistor 7 ₁ are part of a first drivecircuit 10 ₁, which will briefly be referred to as first driver orlow-side driver in the following. This first driver 10 ₁ is configuredto discharge a capacitive load coupled to the output 12. If, as shown inFIG. 1, the load Z is an enhancement MOSFET and has its gate nodecoupled to the output 12 the capacitive load is the internal gate-sourcecapacitance CGS of the MOSFET. Discharging this internal capacitance CGSby the first driver 10 ₁ is equivalent to switching of the MOSFET Z.Thus, if the load Z driven by the electronic drive circuit is an MOStransistor the first driver 10 ₁ is configured to switch off the MOStransistor. Besides the first driver 10 ₁ configured to discharge acapacitive load (switch off an MOS transistor) the electronic circuitmay include a second driver (not shown in FIG. 1) configured to chargethe capacitive load (switch on the MOS transistor).

The first driver 10 ₁ discharges the capacitive load CGS (switches offthe MOS transistor Z) when the output transistor 1 ₁ is in an on-state(is switched on). In the on-state, the output transistor 1 ₁electrically connects the output 12 with the first supply node 13 ₁. Inoperation of the first driver 10 ₁, the first supply 13 ₁ may beconnected to a load terminal of the capacitive load CGS facing away fromthe output 12 so that the load path of the output transistor 10 ₁ isconnected in parallel with the capacitive load CGS.

In general, the operation state of the output transistor 1 ₁ isdependent on operation states of the first electronic switch 3 ₁ and thesecond electronic switch 6 ₁, respectively. The output transistor 1 ₁ isdriven in the on-state when the first electronic switch 3 ₁ switches onand the second electronic switch 6 ₁ switches off, and the outputtransistor 1 ₁ is driven in the off-state when the first electronicswitch 3 ₁ switches off and the second electronic switch 6 ₁ switcheson. The control circuit 8 ₁ is configured to switch the first electronicswitch 3 ₁ and the second electronic switch 6 ₁ based on the inputsignal S_(IN) such that only one of the first electronic switch 3 ₁ andthe second electronic switch 6 ₁ is switched on at the same time. Inorder to prevent a current shoot through, that is, an electricallyconducting path between the first supply node 13 ₁ and the second supplynode 14 ₁, the control circuit 8 ₁ may be configured to drive the firstelectronic switch 3 ₁ and the second electronic switch 6 ₁ such thatthere is a delay time (dead time) between switching off one of the firstelectronic switch 3 ₁ and the second electronic switch 6 ₁ and switchingon the other one of the first electronic switch and the secondelectronic switch 6 ₁.

One way of operation of the control circuit 8 ₁ is shown in FIG. 2. FIG.2 shows timing diagrams of the input signal S_(IN), the drive signal S3₁ of the first electronic switch 3 ₁ and the drive signal S6 ₁ of thesecond electronic switch 6 ₁. The input signal S_(IN) defines thedesired operation state of the load Z driven by the electronic switch10. For the purpose of illustration, it is assumed that the input signalS_(IN) can have one of two different signal levels, namely a firstsignal LE1 and a second signal level LE2. The first signal level LE1indicates that it is desired to switch off the output transistor 1 ₁, soas to prevent the capacitive load CGS from being discharged, and thesecond signal level LE2 indicates that it is desired to switch on theoutput transistor 1 ₁, so as to discharge the capacitive load CGS. Justfor the purpose of illustration, the first level LE1 is a high-level andthe second level LE2 is a low-level in the example shown in FIG. 2.

Each of the drive signals S3 ₁, S6 ₁ can have one of an on-level, whichswitches on the respective electronic switch 3 ₁, 6 ₁, and an off-level,which switches off the respective switch 3 ₁, 6 ₁. When the input signalS_(IN) has the first level LE1 the control circuit 8 ₁ switches off thefirst electronic switch 3 ₁ by generating an off-level of the drivesignal S3 ₁ and switches on the second electronic switch 6 ₁ bygenerating an on-level of the drive signal S6 ₁. In this operation modeof the first driver 10 ₁ the output transistor 1 ₁ is switched off. Whenthe signal level of the input signal S_(IN) changes from the first levelLE1 to the second level LE2 the control circuit 8 ₁ switches off thesecond electronic switch 6 ₁ by generating an off-level of the drivesignal S6 ₁ and, after an optional delay time T_(D), switches on thefirst electronic switch 3 ₁, by generating an on-level of the drivesignal S3 ₁. In this operation mode of the first driver 10 ₁ the outputtransistor 1 ₁ is switched on.

One way of operation of the first driver 10 ₁ shown in FIG. 1 isexplained in the following. For the purpose of explanation, it isassumed that each of the output transistor 1 ₁ and the drive transistor2 ₁ is an n-type MOSFET, in particular, an n-type enhancement MOSFET. Inthis case, the control node of the output transistor 1 ₁ and the drivetransistor 2 ₁, respectively, is the gate node of the MOSFET forming therespective transistor, and the load path is the drain-source path of theMOSFET forming the respective transistor. Referring to FIG. 1, the drainnode of the MOSFET forming the output transistor 1 ₁ (briefly referredto as the drain node of the output transistor 1 ₁ in the following) isconnected to the output 12, and the source node is connected to thefirst supply node 13 ₁. The source node of the MOSFET forming the drivetransistor 2 ₁ (briefly referred to as the source node of the drivetransistor 2 ₁ in the following) is connected to the gate node of theoutput transistor 1 ₁, and the drain node of the drive transistor 2 ₁ isconnected to the first electronic switch 3 ₁.

For the purpose of explanation, it is further assumed that the firstelectronic switch 3 ₁ and the second electronic switch 6 ₁ aretransistors of complementary conductivity types. In the embodiment shownin FIG. 1, the first electronic switch 3 ₁ is a p-type MOSFET, inparticular, a p-type enhancement MOSFET, and the second electronicswitch 6 ₁ is an n-type MOSFET, in particular, an n-type enhancementMOSFET. The MOSFET forming the first electronic switch 3 ₁ receives thedrive signal S3 ₁ from the control circuit 8 ₁ at its gate node. Thedrain node of this MOSFET forming the first electronic switch 3 ₁ isconnected to the drain node of the drive transistor 2 ₁, and the sourcenode of the MOSFET forming the first electronic switch 3 ₁ is connectedto the second supply node 14 ₁. The MOSFET forming the second electronicswitch 6 ₁ receives the drive signal S6 ₁ from the control circuit 8 ₁at its gate node. The drain source path of this MOSFET forming thesecond electronic switch 6 ₁ is connected between the gate node of theoutput transistor 1 ₁ and the first supply node 13 ₁. That is, thedrain-source path of the MOSFET forming the second electronic switch 6 ₁is connected in parallel with an internal gate-source capacitance CGS1 ₁of the output transistor 1 ₁. The output transistor 1 ₁ further includesan internal gate-train capacitance. However, this capacitance is notexplicitly illustrated in FIG. 1.

The drive transistor 2 ₁ includes an internal gate-source capacitanceCGS2 ₁ and an internal gate-drain capacitance CGD2 ₁. In FIG. 1, thesecapacitances are represented by capacitors connected between the gatenode and the source node and the drain node, respectively. VGS2 ₁ andVGD2 ₁ denote voltages across these capacitances CGS2 ₁, CGD2 ₁.

If the first electronic switch 3 ₁ is implemented as a p-type MOSFET,then, the off-level of the drive signal S3 ₁ may correspond to the levelof the electrically potential V2 ₁ at the second supply node 14 ₁, whilethe on-level may be a signal level that is less than the electricallypotential V2 ₁ at the second supply node 14 ₁ minus the thresholdvoltage of this p-type MOSFET 3 ₁. Those signal levels are shown in FIG.2. If the second electronic switch 6 ₁ is an n-type MOSFET, then theoff-level of the drive signal S6 ₁ may correspond to the level of theelectrical potential V1 ₁ at the first supply node 13 ₁, while theon-level may be a signal level that is higher than the electricalpotential V1 ₁ at the first supply node 13 ₁ plus the threshold voltageof this n-type MOSFET. These signal levels are also shown in FIG. 2.

An operation mode of the first driver 10 ₁ in which the outputtransistor 1 ₁ is switched off will be referred to as off-state of thefirst driver 10 ₁, and an operation mode in which the output transistor1 ₁ is switched on will be referred to as on-state of the first driver10 ₁. There are applications in which it is desirable for the firstdriver 10 ₁ to rapidly switch from the off-state to the on-state, thatis, to rapidly switch on the output transistor 1 ₁. Switching on theoutput transistor 1 ₁ includes charging the internal gate-sourcecapacitance CGS1 ₁ such that the gate-source voltage VGS1 ₁ across thisinternal capacitance CGS1 ₁ rises above the threshold voltage of theoutput transistor 1 ₁. In order to rapidly switch on the outputtransistor 1 ₁ it is desirable to rapidly charge the internal gatesource capacitance CGS1 ₁ without causing the voltage VGS1 ₁ to exceed apredefined voltage threshold. The drive transistor 2 ₁, which has itsgate node biased by the biasing circuit 4 ₁, is capable of rapidlycharging the gate-source capacitance CGS1 ₁ of the output transistor 1₁. This is explained below.

When the first electronic switch 1 ₁ is in the off-state and thegate-source capacitance CGS1 ₁ of the output transistor 1 ₁ has beendischarged, then the electrical potential at the source node S2 ₁ of thedrive transistor 2 ₁ corresponds to the electrical potential V1 ₁ at thefirst supply node 13 ₁ so that the gate-source voltage VGS2 ₁ of thedrive transistor 2 ₁ corresponds to the biasing voltage V4 ₁ provided bythe biasing circuit 4 ₁. This biasing voltage V4 ₁ is such that it ishigher than the threshold voltage of the drive transistor 2 ₁ so thatthe drive transistor 2 ₁ is in the on-state. However, a current IDS2 ₁through the drive transistor 2 ₁ is zero until the first electronicswitch 3 ₁ switches on. Before the first electronic switch 3 ₁ switcheson, the electrical potential at the drain node D2 ₁ of the drivetransistor 2 ₁, which is a circuit node between the drive transistor 2 ₁and the first electronic switch 3 ₁, substantially corresponds to theelectrical potential V1 ₁ at the first supply node 13 ₁. Thus, agate-drain-voltage VGD2 ₁ of the drive transistor 2 ₁ also equals thebiasing voltage V4 ₁ provided by the biasing circuit 4 ₁. In FIG. 1, VG2₁ denotes a voltage between the gate node G2 ₁ of the drive transistor 2₁ and the first supply node 13 ₁. This voltage will be referred to asgate voltage in the following. In the steady state, before the firstelectronic switch 3 ₁ switches on, the gate voltage VG2 ₁ substantiallyequals the biasing voltage V4 ₁.

FIG. 3 shows timing diagrams of the drive signal S3 ₁ of the firstelectronic switch 3 ₁, the gate voltage VG2 ₁ of the drive transistor 2₁, the gate-source voltage VGS1 ₁ of the output transistor 1 ₁, and thecurrent IDS1 ₁ through the output transistor 1 ₁. The timing diagramsshown in FIG. 3 begin at a time shortly before the electronic switch 3 ₁switches on. Before the first electronic switch 3 ₁ switches on, thegate-source voltage VGS1 ₁ of the output transistor 1 ₁ is zero, thecurrent IDS1 ₁ (the drain-source current) through the output transistor1 ₁ is zero, and each of the gate voltage VG2 ₁, the gate-source voltageVGS2 ₁, and the gate-drain voltage VGD2 ₁ of the drive transistor 2 ₁substantially equal the biasing voltage V4 ₁.

When the control circuit 8 ₁ switches on the first electronic switch 3 ₁based on the input signal S_(IN) the gate-source capacitance CGS1 ₁ ofthe output transistor 1 ₁ is rapidly charged because the drivetransistor 2 ₁ is already conducting when the first electronic switch 3₁ switches on. The first electronic switch 3 ₁ switches on as soon asthe drive signal S3 ₁ reaches the threshold voltage of the MOSFETforming the first electronic switch 3 ₁. As soon as the drive signal S3₁ reaches the threshold voltage a current IDS2 ₁ with a current leveldefined by the drive transistor 2 ₁ flows through the drive transistor 2₁ and into a gate-source capacitance CGS1 ₁ of the output transistor 1₁. A further increase of the signal level between the gate node and thesource node of the first electronic switch 3 ₁ to above the thresholdvoltage may reduce the losses occurring in the first electronic switchbut does not change the current IDS2 ₁. This is by virtue of the drivetransistor 2 ₁ being pre-biased by the biasing source 4 ₁. The level ofthe current IGS2 ₁ through the drive transistor 2 ₁ is substantiallydefined by the gate-source voltage VGS2 ₁ of the drive transistor 2 ₁.

The current IGD2 ₁ which flows right after the first electronic switch 3₁ switches on, rapidly charges the gate-source capacitance CGS1 ₁ of theoutput transistor 1 ₁, thus causing a rapidly increasing current IDS1 ₁through the output transistor 1 ₁. This current IDS1 ₁ decreases as thecapacitive load CGS is discharged.

Referring to FIG. 3, the gate voltage VG2 ₁ of the drive transistor 2₁—which corresponds to the gate-source voltage VGS2 ₁ before thegate-source capacitance CGS1 ₁ of the output transistor ischarged—increases to a voltage level which is above the level of thebiasing voltage V4 ₁ when the electronic switch 3 ₁ switches on. Thatis,VG2₁ =V4₁ +ΔV  (1),where ΔV is the increase of the gate potential relative to the biasingvoltage V4 ₁. This increase ΔV of the gate voltage VG2 ₁, which is equalVGS2 ₁ at the time of switching on the first electronic switch, resultsin an increase of the current IDS2 ₁ as compared to a scenario in whichthe drive transistor 2 ₁ is only biased by the biasing voltage 41 ₁ Thereason for this increase ΔV in the gate voltage VG2 ₁ is as follows.

Basically, there are two effects that cause the gate voltage VG2 ₁ toincrease. The first effect is based on the fact that the gate node G2 ₁is capacitively coupled to the drain node D2 ₁ through the internalgate-drain capacitance CGD. When the first electronic switch 3 ₁switches on, the electrical potential VD2 ₁ at the drain node D2 ₁ ofthe drive transistor 2 ₁ rises from the first supply potential V1 ₁ tothe second supply potential V2 ₁. By virtue of the capacitive couplingof the gate node G2 ₁ to the drain node D2 ₁ the electrical potential atthe gate node G2 ₁ increases as the electrical potential VD2 ₁ at thedrain node D2 ₁ increases. The internal impedance 42 ₁ of the biasingcircuit 4 ₁ prevents the biasing circuit 4 ₁ from instantaneouslybalancing such increase ΔV of the electrical potential at the gate nodeG2 ₁ of the drive transistor 2 ₁.

According to one embodiment, shown in FIG. 4, the internal impedance 42₁ of the biasing circuit 4 ₁ includes a parallel circuit with a resistor422 ₁ and a capacitor 423 ₁ between the gate node G2 ₁ of the drivetransistor 2 ₁ and the first supply node 13 ₁. The capacitor 432 ₁ ofthe biasing circuit 4 ₁ and the gate-drain capacitance CGD2 ₁ of thedrive transistor 2 ₁ form a capacitive voltage divider. In the steadystate, before the first electronic switch 3 ₁ switches on, the capacitor423 ₁ of the biasing circuit 4 ₁ has been charged to the biasing voltageV4 ₁ and the gate-drain capacitance CGD2 ₁ has been charged to thebiasing voltage V4 ₁. When the electrical potential VD2 ₁ at the drainnode increases the gate voltage VG2 ₁ of the drive transistor 2 ₁increases. It can be shown that right after switching on the firstelectronic switch 3 ₁ an increase ΔV′ of the gate voltage VG2 ₁, as afirst approximation, is as follows:

$\begin{matrix}{{{\Delta\; V^{\prime}} = {\frac{{CGD}\; 2_{1}}{{{CGD}\; 2_{1}} + {C\; 423_{1}}} \cdot \left( {{V\; 2_{1}} - {V\; 1_{1}}} \right)}},} & (2)\end{matrix}$where C423 ₁ is the capacitance of the capacitor, CGD2 ₁ is thecapacitance value of the gate-drain capacitance. This firstapproximation neglects the gate-source capacitance CGS2 ₁ of the drivetransistor, that is, it is based on the assumption that the capacitivevoltage divider between the drain node D2 ₁ and the first supply nodeonly includes the gate-drain capacitance CGD2 ₁ and the capacitor 423 ₁.If, however, the capacitance of the capacitor 423 ₁ is significantlyhigher than the gate-drain capacitance CGD2 ₁ this assumption is valid.If the gate-source capacitance CGS2 ₁ is taken into accountadditionally, the voltage increase ΔV′ is less than the value obtainedby applying equation (2). Referring to equation (2), the voltagedifference ΔV′ can be adjusted by suitably designing the capacitanceC423 ₁ of the capacitor 423 ₁ relative to the capacitance value of thegate-drain capacitance CGD2 ₁.

After switching on the first electronic switch 3 ₁, an increase of thedrive transistor's gate potential VG2 ₁ to above the level of thebiasing voltage V4 ₁ is not only caused by the increase of the drainpotential VG2 ₁ of the drive transistor 2 ₁, but is also caused by anincrease of the gate-source voltage VGS1 ₁ of the output transistor 1 ₁.This is a second effect that causes an increase of the gate voltage VG2₁. The gate node of the output transistor 1 ₁ is capacitively coupled tothe gate node G2 ₁ of the drive transistor 2 ₁ via the gate-sourcecapacitance CGS2 ₁ of the drive transistor 2 ₁, so that an increase ofthe gate-source voltage VGS1 ₁ of the output transistor 1 ₁ causes anincrease of the gate potential VG2 ₁ of the drive transistor 2 ₁. As afirst approximation, that neglects the gate-drain capacitance CGD2 ₁, anincrease ΔV″ of the gate potential VG2 ₁ resulting from this effect isgiven as follows:

$\begin{matrix}{{{\Delta\; V^{''}} = {{\frac{{CGS}\; 2_{1}}{{{CGS}\; 2_{1}} + {C\; 423_{1}}} \cdot {VGS}}\; 1_{1}}},} & (3)\end{matrix}$where VGS1 ₁ denotes the voltage level of the output transistorsgate-source voltage, CGS2 ₁ denotes the capacitance value of the drivetransistor's 2 ₁ gate-source capacitance, and C423 ₁ denotes thecapacitance of the capacitor 423 ₁ in the biasing circuit 4 ₁. Based onequation (3) it can be seen that by suitably designing the capacitanceof the capacitor 423 ₁ relative to the capacitance value of thegate-source capacitance CGS2 ₁ of the drive transistor 2 ₁ the increaseΔV″ of the gate potential VG2 ₁ can be limited.

The overall increase ΔV of the gate voltage VG2 ₁ referred to inequation (1) takes into account both of the effects explained withreference to equations (2) and (3). According to one embodiment, thecapacitance C423 ₁ is adapted to capacitance values of the gate-draincapacitance CGD2 ₁ and the gate-source capacitance CGS2 ₁ and to thevoltage swings at the drain node D2 ₁ and the source node S2 ₁ of thedrive transistor such that overall increase ΔV of the gate voltage VG2 ₁is between 5% and 25%, in particular between 10% and 20% of the biasingvoltage V4 ₁. According to one embodiment, the capacitance C423 ₁ of thecapacitor 423 ₁ is at least 10 times, in particular at least 50 timesthe maximum capacitance value of the gate-drain capacitance CGD2 ₁.According to one embodiment, the capacitance C423 ₁ of the capacitor 423₁ is at least 5 times, in particular at least 10 times the maximumcapacitance value of the gate-source capacitance CGS2 ₁.

The supply voltage V2 ₁−V1 ₁ between the second supply node 14 ₁ and thefirst supply node 13 ₁ is higher than the biasing voltage V4 ₁.According to one embodiment, the supply voltage is at least 2 times, atleast 3 times, or even at least 5 times the biasing voltage. Accordingto one embodiment, the biasing voltage V4 ₁ is between 2.5V and 3.5Vwhile the supply voltage is 10V or higher.

Referring to FIG. 3 the gate-source voltage VGS1 ₁ of the outputtransistor 1 ₁ is below the electrical potential VG2 ₁ at the gate nodeof the drive transistor 2 ₁ because the drive transistor 2 ₁ switchesoff when the gate-source voltage VGS1 ₁ of the output transistor 1 ₁reaches a voltage level that equals the electrical potential VG2 ₁ atthe gate node G2 ₁ of the drive transistor 2 ₁ minus the thresholdvoltage of the drive transistor 2 ₁. Thus, the gate-source voltage VGS1₁ of the output transistor 1 ₁ is always lower than the biasing voltageV4 ₁ plus the voltage difference ΔV so that the maximum gate-sourcevoltage VGS1 ₁ of the output transistor can be adjusted by suitablydesigning the biasing circuit 41 ₁ in particular, by suitably selectingthe biasing voltage V4 ₁ and the capacitor 423 ₁. In the biasing circuit4 ₁, the resistor 422 ₁ connected in parallel with the capacitor 423 ₁discharges the capacitor 423 ₁ so that a voltage level of the gatevoltage VG2 ₁ gradually decrease to the level of the biasing voltage V4₁. The rate at which the gate potential VG2 ₁ decreases is dependent onthe time constant of the parallel circuit with the resistor 422 ₁ andthe capacitor 423 ₁. In general, the rate at which the gate potentialVG2 ₁ decreases is the higher the lower a resistance R422 ₁ of theresistor 422 ₁ is, and vice versa.

Referring to FIG. 4, the internal impedance 42 ₁ includes a furtherresistor 421 ₁ connected between the voltage source 41 ₁ and the gatenode G2 ₁ of the drive transistor 2 ₁. This further resistor 421 ₁defines the biasing circuit's 4 ₁ capability to counteract a decrease ofthe gate potential VG2 ₁ to below the biasing voltage V4 ₁. The lower aresistance R421 ₁ of this resistor 421 ₁ is the faster the biasingcircuit 4 ₁ regulates the gate potential V2 ₁ from a level of below thebiasing voltage V4 ₁ to a level corresponding to the biasing voltage V4₁.

FIG. 5 shows one embodiment of the voltage source 41 ₁ in the biasingcircuit 4 ₁ in greater detail. In this embodiment, the voltage source 41₁ is implemented as a linear voltage regulator connected between thefirst supply node 13 ₁ and the second supply node 14 ₁. In thisembodiment, the voltage regulator includes an output transistor 411 ₁that has a load path connected between the second supply node 14 ₁ andthe parallel circuit with the resistor 422 ₁ and the capacitor 423 ₁.The further resistor 421 ₁ shown in FIG. 4 is defined by thecharacteristic of the output transistor 411 ₁ in the embodiment shown inFIG. 5. In particular, the resistor is defined by the transconductance,often referred to as gm, of the output transistor 422 ₁. In theembodiment shown in FIG. 5, the output transistor 411 ₁ is implementedas a MOSFET, in particular as an n-type MOSFET. In this voltageregulator 41 ₁, the output transistor 411 ₁ is driven such that, in thesteady state, the voltage across the parallel circuit with the resistor422 ₁ and the capacitor 423 ₁ corresponds to the biasing voltage V4 ₁.This biasing voltage V4 ₁ is defined by a reference current source 412 ₁and a further resistor 414 ₁. The reference current source 412 ₁ drivesa reference current I412 ₁ through the resistor 414 ₁ and a MOSFET 415 ₁that has its gate node connected to its drain node. A series circuitwith the further resistor 414 ₁ and the further transistor 415 ₁ isconnected between the gate node of the output transistor 411 ₁ and thefirst supply node 13 ₁. According to one embodiment a resistance of thefurther resistor 414 ₁ equals a resistance of the resistor 422 ₁ and theoutput transistor 411 ₁ and the further transistor 415 ₁ are transistorsof the same type, in particular, of the same channel width, the samechannel length and the same threshold voltage. In this case, thegate-source voltage of the further transistor 415 ₁ and the gate-sourcevoltage of the output transistor 411 ₁ are equal, and a voltage V414 ₁across the further resistor corresponds to the biasing voltage V4 ₁.That is, the biasing voltage V4 ₁ is defined by the level of thereference current I412 ₁ multiplied with a resistance R414 ₁ of thefurther resistor 414 ₁:V414₁ =V4₁ =I412₁ ·R414₁  (4).

Referring to FIG. 5, a capacitor 413 ₁ may be connected in parallel withthe series circuit including the resistor 414 ₁ and the transistor 415₁. Referring to the above, the voltage across the series circuit withthe resistor 414 ₁ and the transistor 415 ₁ is a reference voltage thatdrives the transistor and defines the biasing voltage V4 ₁. The gatenode of the output transistor 411 ₁ is capacitively coupled with theoutput of the voltage regulator 41 ₁, that is, with the parallel circuitincluding the resistor 422 ₁ and the capacitor 423 ₁. Thus, rapidchanges of the biasing voltage V4 ₁, such as the increase of the biasingvoltage at the time of switching on the first electronic switch 3 ₁, maychange the electrical potential at the gate node of the outputtransistor 411 ₁ and, therefore, the reference voltage if no additionalmeasures are taken. The capacitor 413 ₁ filters such changes of theelectrical potential at the gate node of the output transistor 411 ₁and, therefore, stabilizes the reference voltage.

The electronic circuit 1 with the first driver 10 ₁ explained above isconfigured to discharge a capacitive load CGS connected to output 12.FIG. 6 shows one embodiment of an electronic drive circuit that isconfigured to charge a capacitive load CGS connected to the output 12based on an input signal S_(IN). Like in the embodiment shown in FIG. 1,the capacitive load is a gate-source capacitance of a MOSFET Z.

The electronic circuit shown in FIG. 6 includes a driver 10 ₂, whichwill be referred to as second driver or high-side driver in thefollowing. The tropology of the driver 10 ₂ corresponds to the tropologyof the driver 10 ₁ shown in FIG. 1 to which reference is made. In thedrivers 10 ₁, 10 ₂ shown in FIGS. 1 and 6 like features have the samereference characters that are only different by a subscript index “1”added to the reference characters in FIG. 1 and a subscript index “2”added to the reference characters in FIG. 6. In particular, the driver10 ₂ shown in FIG. 6 an output transistor 1 ₂, a drive transistor 2 ₂,and a first electronic switch 3 ₂. The output transistor 1 ₂ includes acontrol node and a load path connected between the output 12 and a firstsupply node 13 ₂. The drive transistor 2 ₁ includes a control node, anda load path connected to the control node of the output transistor 1 ₂and connected in series with the first electronic switch 3 ₂. The firstelectronic switch 3 ₂ is connected between a second supply node 14 ₁ andthe load path of the drive transistor 2 ₁.

The driver 10 ₂ may include a second electronic switch 6 ₂ connectedbetween the control node of the output transistor 1 ₂ and the firstsupply node 13 ₂. Optionally, a resistor 7 ₂ (illustrated in dashedlines in FIG. 6) is connected in parallel with the second electronicswitch 6 ₂ and, therefore, between the control node of the outputtransistor 1 ₂ and the first supply node 13 ₂.

A biasing circuit 4 ₂ is connected between the control node of the drivetransistor 2 ₂ and the first supply node 13 ₂. The biasing circuit 4 ₂includes a voltage source 41 ₂ configured to provide a biasing voltageV4 ₂, and an internal impedance 42 ₂. A control circuit 5 ₂ isconfigured to receive the input signal S_(IN) and to drive the firstelectronic switch 3 ₂ and the second electronic switch 6 ₂ based on theinput signal S_(IN).

Referring to FIG. 7, which shows timing diagrams of the input SignalS_(IN), a drive signal S3 ₂ of the first electronic switch 3 ₂, and adrive signal S6 ₂ of the second electronic switch 6 ₂. The input signalS_(IN) defines the desired operation state of the load Z driven by theelectronic switch 10. For the purpose of illustration, it is assumedthat the input signal S_(IN) can have one of two different signallevels, namely a first signal LE1 and a second signal level LE2. Thefirst signal level LE1 indicates that it is desired to switch on theoutput transistor 1 ₂, so as to charge the capacitive load CGS, and thesecond signal level LE2 indicates that it is desired to switch off theoutput transistor 1 ₂. Just for the purpose of illustration, the firstlevel LE1 is a high-level and the second level LE2 is a low-level in theexample shown in FIG. 7.

Each of the drive signals S3 ₂, S6 ₂ can have one of an on-level, whichswitches on the respective electronic switch 3 ₂, 6 ₂, and an off-level,which switches off the respective switch 3 ₂, 6 ₂. When the input signalS_(IN) has the second level LE2 the control circuit 8 ₂ switches off thefirst electronic switch 3 ₂ by generating an off-level of the drivesignal S3 ₂ and switches on the second electronic switch 6 ₂ bygenerating an on-level of the drive signal S6 ₂. In this operation modeof the first driver 10 ₂ the output transistor 1 ₂ is switched off. Whenthe signal level of the input signal S_(IN) changes from the secondlevel LE2 to the first level LE1 the control circuit 8 ₂ switches offthe second electronic switch 6 ₂ by generating an off-level of the drivesignal S6 ₂ and, after an optional delay time T_(D), switches on thefirst electronic switch 3 ₂, by generating an on-level of the drivesignal S3 ₂. In this operation mode of the first driver 10 ₂ the outputtransistor 1 ₂ is switched on.

The driver 10 ₂ shown in FIG. 6 is different from the driver 10 ₁ shownin FIG. 1 in that the output transistor 1 ₂ and the drive transistor 2 ₂are p-type MOSFETs, wherein the drain node of the output transistor 1 ₂is connected to the output 12, and the source node of the drivetransistor 2 ₂ is connected to the gate of the output transistor 1 ₂.Further, the first electronic switch 3 ₂ is an n-type MOSFET and thesecond electronic switch 6 ₂ is a p-type MOSFET, wherein a source nodeof the MOSFET forming the first electronic switch 3 ₂ is connected tothe second supply node 14 ₂. Furthermore, an electrical potential V1 ₂at the first supply node 13 ₂ is higher than an electrical potential V2₂ at the second supply node 14 ₂.

If, in the driver 10 ₂ shown in FIG. 6, the first electronic switch 3 ₂is implemented as an n-type MOSFET, then the off-level of the drivesignal S3 ₁ may correspond to the level of the electrically potential V2₂ at the second supply node 14 ₂, while the on-level may be a signallevel that is higher than the electrically potential V2 ₂ at the secondsupply node 14 ₂ plus the threshold voltage of this n-type MOSFET 3 ₂.Those signal levels are shown in FIG. 7. If the second electronic switch6 ₂ is a p-type MOSFET, then the off-level of the drive signal S6 ₁ maycorrespond to the level of the electrical potential V1 ₁ at the firstsupply node 13 ₁, while the on-level may be a signal level that is lowerthan the electrical potential V1 ₂ at the first supply node 13 ₂ minusthe threshold voltage of this p-type MOSFET. These signal levels arealso shown in FIG. 7.

Everything that has been explained with regard to the functionality ofthe first driver 10 ₁ shown in FIG. 1 applies to the second driver 10 ₂shown in FIG. 6 as well. In particular, at the time of switching on thefirst switch 3 ₁ the magnitude of the gate voltage VG2 ₂ of the drivetransistor 2 ₂ increases to above the magnitude of the biasing voltageby virtue of the capacitive coupling of the gate node G2 ₂ to the drainnode D2 ₂ and the source node S2 ₂, respectively, and by virtue of theinternal impedance 42 ₂ of the biasing source 4 ₂. The biasing sourcemay be implemented as explained with reference to FIGS. 4 and 5 hereinbelow, wherein the output transistor (not shown) in the biasing source 4₂ may be implemented as a p-type transistor instead of the n-typetransistor 411 ₁ shown in FIG. 5.

FIG. 8 shows one embodiment of an electronic switch that includes a lowside driver 10 ₁ as shown in FIG. 1 and a high side driver 10 ₂ as shownin FIG. 6. This electronic circuit is configured to charge thecapacitive load CGS or discharge the capacitive load based on the inputsignal. In this embodiment, the second supply node 14 ₁ of the low sidedriver 10 ₁ is connected to the first supply node 13 ₂ of the high sidedriver 10 ₂ so that the second supply potential V2 ₁ of the low-sidedriver 10 ₁ equals the first supply potential V1 ₂ of the high-sidedriver 10 ₂, that is, V2 ₁=V1 ₂=V2. Furthermore, the second supply node14 ₂ of the high side driver 10 ₂ is connected to the first supply node13 ₁ of the low side driver 10 ₁ so that the second supply potential V2₂ of the high-side driver 10 ₂ equals the first supply potential V1 ₁ ofthe low-side driver, that is, V2 ₂=V1 ₁=V1. V1 denotes of an electricalpotential received at the first supply node 13 ₁ (the second supply node142) of the low side driver 10 ₁ (the high side driver 10 ₂), and V2denotes an electrical potential received at the second supply node 14 ₁(the first supply node 13 ₂) of the low side driver 10 ₁ (the high sidedriver 10 ₂). The electrical potential V1 may correspond to theelectrical potential at a load terminal of the capacitive load CGSfacing away from the output 12.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. An electronic circuit, comprising: an inputconfigured to receive an input signal and an output configured to becoupled to a load; an output transistor comprising a load path and acontrol node, the load path being connected between the output and afirst supply node; a drive transistor comprising a load path and acontrol node, the load path of the drive transistor being connected tothe control node of the output transistor; a first electronic switchconnected in series with the load path of the drive transistor; abiasing circuit comprising an internal impedance and connected betweenthe control node of the drive transistor and the first supply node; anda control circuit configured to receive the input signal and to generatea first drive signal for driving the first electronic switch based onthe input signal, the first drive signal having an on-level and anoff-level which depend on a state of the input signal.
 2. The electroniccircuit of claim 1, wherein the first electronic switch is connectedbetween the load path of the drive transistor and a second supply node.3. The electronic circuit of claim 1, further comprising: a secondelectronic switch connected between the control node of the outputtransistor and the first supply node, wherein the control circuit isconfigured to generate a second drive signal for driving the secondelectronic switch based on the input signal, the second drive signalhaving an on-level and an off-level which depend on the state of theinput signal.
 4. The electronic circuit of claim 3, wherein the controlcircuit is configured to drive the first electronic switch and thesecond electronic switch such that at most one of the first electronicswitch and the second electronic switch is driven in an on-state at thesame time.
 5. The electronic circuit of claim 1, further comprising: aresistor connected between the control node of the output transistor andthe first supply node.
 6. The electronic circuit of claim 1, wherein theinternal impedance of the biasing circuit comprises at least one of aresistor and a capacitor connected between the control node of the drivetransistor and the first supply node.
 7. The electronic circuit of claim6, wherein the drive transistor has an internal gate-drain capacitance,and wherein a capacitance of the capacitor is at least 10 times acapacitance value of the gate-drain capacitance.
 8. The electroniccircuit of claim 6, wherein the drive transistor has an internalgate-source capacitance, and wherein a capacitance of the capacitor isat least 5 times a capacitance value of the gate-source capacitance. 9.The electronic circuit of claim 1, wherein the output transistor and thedrive transistor have the same conductivity type.
 10. The electroniccircuit of claim 9, wherein the first electronic switch is implementedas a transistor of a conductivity type complementary to the conductivitytype of the output transistor and the drive transistor.
 11. Theelectronic circuit of claim 1, wherein the biasing circuit furthercomprises a voltage regulator having a supply input connected betweenthe first supply node and a second supply node, and having an outputcoupled to the control node of the drive transistor.
 12. The electroniccircuit of claim 2, wherein the first supply node is configured toreceive a first electrical potential and the second supply node isconfigured to receive a second electrical potential higher than thefirst electrical potential, wherein each of the output transistor andthe drive transistor is an n-type MOSFET, and wherein the firstelectronic switch is a p-type MOSFET.
 13. The electronic circuit ofclaim 2, wherein the first supply node is configured to receive a firstelectrical potential and the second supply node is configured to receivea second electrical potential lower than the first electrical potential,wherein each of the output transistor and the drive transistor is ap-type MOSFET, and wherein the first electronic switch is an n-typeMOSFET.
 14. The electronic circuit of claim 2, further comprising: afurther output transistor comprising a load path and a control node, theload path being connected between the output and a third supply node; afurther drive transistor comprising a load path and a control node, theload path being connected to the control node of the further outputtransistor; a further first electronic switch connected in series withthe load path of the further drive transistor; a further biasing circuitcomprising an internal impedance and connected between the control nodeof the further drive transistor and the third supply node; and a furthercontrol circuit configured to receive the input signal and to drive thefurther first electronic switch based on the input signal.
 15. Theelectronic circuit of claim 14, wherein the further first electronicswitch is connected between the load path of the further drivetransistor and a fourth supply node.
 16. The electronic circuit of claim15, wherein the first supply node and the fourth supply node areconnected and the second supply node and the third supply node areconnected.
 17. The electronic circuit of claim 14, further comprising: afurther second electronic switch connected between the control node ofthe output transistor and the third supply node, wherein the furthercontrol circuit is configured to drive the second electronic switchbased on the input signal.
 18. The electronic circuit of claim 17,wherein the control circuit is configured to drive the further firstelectronic switch and the further second electronic switch such that atmost one of the further first electronic switch and the further secondelectronic switch is driven in an on-state at the same time.
 19. Theelectronic circuit of claim 14, further comprising: a further resistorconnected between the control node of the further output transistor andthe third supply node.
 20. An electronic circuit, comprising: an inputconfigured to receive an input signal and an output configured to becoupled to a load; an output transistor comprising a load path and acontrol node, the load path being connected between the output and afirst supply node; a drive transistor comprising a load path and acontrol node, the load path of the drive transistor being connected tothe control node of the output transistor; a first electronic switchconnected in series with the load path of the drive transistor; abiasing circuit comprising an internal impedance and connected betweenthe control node of the drive transistor and the first supply node; anda control circuit configured to receive the input signal and to drivethe first electronic switch based on the input signal, wherein thebiasing circuit further comprises a voltage regulator having a supplyinput connected between the first supply node and a second supply node,and having an output coupled to the control node of the drivetransistor.